论文标题
用chiplet架构缩放超导量子计算机
Scaling Superconducting Quantum Computers with Chiplet Architectures
论文作者
论文摘要
固定频率的Transmon量子计算机(QC)在相干时间,可寻址性和门票方面具有进步。不幸的是,这些设备受片上Qubit的数量,封盖处理能力的限制,并放缓了耐受耐受性的进度。尽管新兴的Transmon设备具有100吨以上的功能,但构建QCS足以有意义的量子优势证明需要克服许多设计挑战。例如,由于制造精度有限,当今的Transmon Qubits遭受了显着差异。结果,除非当前制造技术取得显着改进,否则通过设备变化来阻碍使用更多Qubit的较大的单个芯片来扩展QC。降低质量控制性能的严重设备变化被称为缺陷。在这里,我们专注于称为频率碰撞的特定缺陷。 当Transmon频率发生碰撞时,它们的差异落在限制两个Qubit Gate Fidelity的范围内。频率碰撞发生在较大的QC上的可能性更大,从而导致无碰撞的产量下降,随着芯片量子的数量增加。作为解决方案,我们建议通过在量子多芯片模块(MCMS)中整合量子芯片来利用与较小的QC相关的较高产量。产量,栅极性能和基于应用程序的分析显示了QC通过模块化的可行性。
Fixed-frequency transmon quantum computers (QCs) have advanced in coherence times, addressability, and gate fidelities. Unfortunately, these devices are restricted by the number of on-chip qubits, capping processing power and slowing progress toward fault-tolerance. Although emerging transmon devices feature over 100 qubits, building QCs large enough for meaningful demonstrations of quantum advantage requires overcoming many design challenges. For example, today's transmon qubits suffer from significant variation due to limited precision in fabrication. As a result, barring significant improvements in current fabrication techniques, scaling QCs by building ever larger individual chips with more qubits is hampered by device variation. Severe device variation that degrades QC performance is referred to as a defect. Here, we focus on a specific defect known as a frequency collision. When transmon frequencies collide, their difference falls within a range that limits two-qubit gate fidelity. Frequency collisions occur with greater probability on larger QCs, causing collision-free yields to decline as the number of on-chip qubits increases. As a solution, we propose exploiting the higher yields associated with smaller QCs by integrating quantum chiplets within quantum multi-chip modules (MCMs). Yield, gate performance, and application-based analysis show the feasibility of QC scaling through modularity.