论文标题
PEF：基于泊松方程的大规模固定外线平面图
PeF: Poisson's Equation Based Large-Scale Fixed-Outline Floorplanning
论文作者
论文摘要
平面图是VLSI物理设计的第一阶段。有效的平面图肯定会对芯片设计速度，质量和性能产生积极影响。在本文中，我们提出了一个新颖的数学模型，以表征模块的非重叠，并根据使用Poisson方程的VLSI全球放置方法提出了一种平坦的固定外面平面图算法。该算法由全球平面图和合法化阶段组成。在全球平面图中，我们基于新的数学模型来重新定义每个模块的势能，以表征模块的非重叠和泊松方程的分析解决方案。在此方案中，软模块的宽度显示为能量函数中的变量，并且可以优化。此外，我们为势能的部分导数设计了快速近似计算方案。在合法化中，基于定义的水平和垂直约束图，我们通过修改模块的相对位置来消除整体平面图后仍保留的模块之间的重叠。在MCNC，GSRC，HB+和AMI49 \ _x基准上进行的实验表明，与某些白色的算法相比，在小型和大型基准上，我们的算法将平均电线长度至少提高了2 \％和5％，而小型和大型基准分别将其提高，而不是一定的白色。
Floorplanning is the first stage of VLSI physical design. An effective floorplanning engine definitely has positive impact on chip design speed, quality and performance. In this paper, we present a novel mathematical model to characterize non-overlapping of modules, and propose a flat fixed-outline floorplanning algorithm based on the VLSI global placement approach using Poisson's equation. The algorithm consists of global floorplanning and legalization phases. In global floorplanning, we redefine the potential energy of each module based on the novel mathematical model for characterizing non-overlapping of modules and an analytical solution of Poisson's equation. In this scheme, the widths of soft modules appear as variables in the energy function and can be optimized. Moreover, we design a fast approximate computation scheme for partial derivatives of the potential energy. In legalization, based on the defined horizontal and vertical constraint graphs, we eliminate overlaps between modules remained after global floorplanning, by modifying relative positions of modules. Experiments on the MCNC, GSRC, HB+ and ami49\_x benchmarks show that, our algorithm improves the average wirelength by at least 2\% and 5\% on small and large scale benchmarks with certain whitespace, respectively, compared to state-of-the-art floorplanners.
