论文标题
智能：研究阈值电压抑制在SRAM乘法/积累加速器中的影响，以改善65 nm CMOS技术
SMART: Investigating the Impact of Threshold Voltage Suppression in an In-SRAM Multiplication/Accumulation Accelerator for Accuracy Improvement in 65 nm CMOS Technology
论文作者
论文摘要
最新的内存计算最近已成为克服与当前计算系统中数据移动相关的设计挑战的最有希望的解决方案。执行内存计算的方法之一是基于存储单元内存储的数据的模拟行为。这些方法为此提出了各种系统体系结构。在本文中，我们研究了阈值抑制对SRAM乘法和积累（MAC）加速器的访问晶体管的影响，以改善和提高位线线（位线条）放电率的性能，从而提高MAC运行的准确性。我们提供了全面的分析分析，然后进行了电路实施，包括65nm CMOS技术的蒙特卡罗模拟。我们确认了四乘四位Mac操作的方法（SMART）的效率。提出的技术可提高每次计算1V电源的0.683 PJ的精度。我们的新技术对最坏情况不正确的输出方案的标准偏差不到0.009。
State-of-the-art in-memory computation has recently emerged as the most promising solution to overcome design challenges related to data movement inside current computing systems. One of the approaches to performing in-memory computation is based on the analog behavior of the data stored inside the memory cell. These approaches proposed various system architectures for that. In this paper, we investigated the effect of threshold voltage suppression on the access transistors of the In-SRAM multiplication and accumulation (MAC) accelerator to improve and enhance the performance of bit line (bit line bar) discharge rate that will increase the accuracy of MAC operation. We provide a comprehensive analytical analysis followed by circuit implementation, including a Monte-Carlo simulation by a 65nm CMOS technology. We confirmed the efficiency of our method (SMART) for a four-by-four-bit MAC operation. The proposed technique improves the accuracy while consuming 0.683 pJ per computation from a power supply of 1V. Our novel technique presents less than 0.009 standard deviations for the worst-case incorrect output scenario.
