论文标题
FPGA随机数生成器
FPGA Random Number Generator
论文作者
论文摘要
随机数生成是一项关键技术，以多种方式有用。随机数通常用于生成用于数据加密的密钥。以足够长的长度生成的随机数可以加密敏感数据，并使另一台计算机或人员很难解密数据。随机数的其他用途包括统计抽样，搜索/排序算法，游戏和赌博。由于随机数的广泛应用程序，因此创建一种可靠地生成随机数的方法将在硬件中可靠地生成随机数，以生成现成的随机数量，以便为任何最终应用程序生成随机数。本文提供了概念验证，用于创建基于Verilog的硬件设计，该硬件设计利用随机测量和争夺算法来同步生成32位随机，并在现场可编程可编程的门阵（FPGA）上单个时钟周期同步。
Random number generation is a key technology that is useful in a variety of ways. Random numbers are often used to generate keys for data encryption. Random numbers generated at a sufficiently long length can encrypt sensitive data and make it difficult for another computer or person to decrypt the data. Other uses for random numbers include statistical sampling, search/sort algorithms, gaming, and gambling. Due to the wide array of applications for random numbers, it would be useful to create a method of generating random numbers reliably directly in hardware to generate a ready supply of a random number for whatever the end application may be. This paper offers a proof-of-concept for creating a verilog-based hardware design that utilizes random measurement and scrambling algorithms to generate 32-bit random synchronously with a single clock cycle on a field-programmable-gate-array(FPGA).
