论文标题
使用部分重新配置在FPGA中进行抢先调度的编程摘要
Programming abstractions for preemptive scheduling in FPGAs using partial reconfiguration
论文作者
论文摘要
FPGA是全能HPC计算系统的一种有吸引力的加速器类型，因为可能会按需部署量身定制的硬件。但是，编程和操作FPGA的常见工具仍然很复杂，特别是在应动态执行各种任务的情况下。在这项工作中，我们介绍了一个简单的接口，它可以内部利用高级合成，动态的部分重新配置和同步机制，以使用FPGA作为具有先发制度调度和优先级的多任务服务器。这可以更好地利用FPGA资源，从而同时执行多个内核，并尽快部署最紧迫的内核。我们的实验研究结果表明，我们的方法仅使用一个可重新配置区域（RR）时只会产生1.66％的开销，而使用两种RR时，我们的方法仅会产生4.04％的速度，同时对传统的非夺取性全面重新配置方法的性能有了显着改善。
FPGAs are an attractive type of accelerator for all-purpose HPC computing systems due to the possibility of deploying tailored hardware on demand. However, the common tools for programming and operating FPGAs are still complex to use, specially in scenarios where diverse types of tasks should be dynamically executed. In this work we present a programming abstraction with a simple interface that internally leverages High-Level Synthesis, Dynamic Partial Reconfiguration and synchronisation mechanisms to use an FPGA as a multi-tasking server with preemptive scheduling and priority queues. This leads to a better use of the FPGA resources, allowing the execution of several kernels at the same time and deploying the most urgent ones as fast as possible. The results of our experimental study show that our approach incurs only a 1.66% overhead when using only one Reconfigurable Region (RR), and 4.04% when using two RRs, whilst presenting a significant performance improvement over the traditional non-preemptive full reconfiguration approach.
