论文标题
样品和汇总图神经网络中采样算法的硬件加速度
Hardware Acceleration of Sampling Algorithms in Sample and Aggregate Graph Neural Networks
论文作者
论文摘要
在许多GNN结构中，采样是一个重要的过程，以训练具有较小计算复杂性的较大数据集。但是，与GNN中的其他过程相比（例如骨料，向后传播），抽样过程仍然需要巨大的时间，这限制了训练速度。为了减少抽样时间，硬件加速度是理想的选择。但是，GNN加速提案的最新状态并未指定如何加速采样过程。更重要的是，直接加速传统抽样算法将使加速器的结构变得非常复杂。 在这项工作中，我们做出了两个贡献：（1）提出了一个新的邻居采样器：Concat Sampler，可以在硬件级别上轻松加速，同时保证测试准确性。 （2）基于FPGA设计了一个Concat-Smplim-Accelerator，与没有它的采样过程相比，邻居采样过程将其提高到约300-1000倍。
Sampling is an important process in many GNN structures in order to train larger datasets with a smaller computational complexity. However, compared to other processes in GNN (such as aggregate, backward propagation), the sampling process still costs tremendous time, which limits the speed of training. To reduce the time of sampling, hardware acceleration is an ideal choice. However, state of the art GNN acceleration proposal did not specify how to accelerate the sampling process. What's more, directly accelerating traditional sampling algorithms will make the structure of the accelerator very complicated. In this work, we made two contributions: (1) Proposed a new neighbor sampler: CONCAT Sampler, which can be easily accelerated on hardware level while guaranteeing the test accuracy. (2) Designed a CONCAT-sampler-accelerator based on FPGA, with which the neighbor sampling process boosted to about 300-1000 times faster compared to the sampling process without it.
