论文标题
固定功能组合逻辑的有效汇编和映射到靶向神经网络推理并利用高级合成的数字信号处理器上
Efficient Compilation and Mapping of Fixed Function Combinational Logic onto Digital Signal Processors Targeting Neural Network Inference and Utilizing High-level Synthesis
论文作者
论文摘要
最新的努力改善了满足当今应用要求的神经网络（NN）加速器的性能，这引起了基于逻辑NN推理的新趋势，该趋势依赖于固定功能组合逻辑。将如此大的布尔功能与许多输入变量和产品术语映射到现场可编程的门阵列（FPGA）上的数字信号处理器（DSP）需要一个新颖的框架，考虑到此过程中DSP块的结构和可重构性。本文中提出的方法将固定函数组合逻辑块映射到一组布尔功能，其中与每个功能相对应的布尔操作映射到DSP设备，而不是FPGA上的查找表（LUTS），以利用DSP块的高性能，低延迟，低延迟和平行词。 ％ 本文还提出了一种创新的设计和优化方法，用于使用高级合成流，利用固定函数组合逻辑与dsps进行DSP。 ％ 我们在几个\ revone {dataSets}和选定的NN上进行的实验评估证明了我们的框架的可比性能，而与先前的基于ART FPGA的NN加速器相比，我们的推断潜伏期和输出准确性具有可比性的性能。
Recent efforts for improving the performance of neural network (NN) accelerators that meet today's application requirements have given rise to a new trend of logic-based NN inference relying on fixed function combinational logic. Mapping such large Boolean functions with many input variables and product terms to digital signal processors (DSPs) on Field-programmable gate arrays (FPGAs) needs a novel framework considering the structure and the reconfigurability of DSP blocks during this process. The proposed methodology in this paper maps the fixed function combinational logic blocks to a set of Boolean functions where Boolean operations corresponding to each function are mapped to DSP devices rather than look-up tables (LUTs) on the FPGAs to take advantage of the high performance, low latency, and parallelism of DSP blocks. % This paper also presents an innovative design and optimization methodology for compilation and mapping of NNs, utilizing fixed function combinational logic to DSPs on FPGAs employing high-level synthesis flow. % Our experimental evaluations across several \REVone{datasets} and selected NNs demonstrate the comparable performance of our framework in terms of the inference latency and output accuracy compared to prior art FPGA-based NN accelerators employing DSPs.
