论文标题
高吞吐量事件的硬件体系结构使用IIR过滤算法的矩阵进行视觉数据过滤
Hardware architecture for high throughput event visual data filtering with matrix of IIR filters algorithm
论文作者
论文摘要
神经形态视觉是一个快速增长的领域，在自动驾驶汽车的感知系统中有许多应用。不幸的是，由于传感器的工作原理，事件流中有很大的噪声。在本文中，我们提出了一种基于IIR滤波器矩阵的新算法，用于过滤这种类型的噪声和硬件体系结构，可使用SOC FPGA加速。我们的方法具有非常好的过滤效率，可用于不相关的噪声 - 超过99％的嘈杂事件被删除。已经对几个事件数据集进行了测试，并增加了随机噪声。我们设计了硬件体系结构，以减少FPGA内部BRAM资源的利用。这使得每秒的潜伏期非常低，最多可达3858元MERP的事件。在模拟和Xilinx Zynx Zynx Ultrascale+ mpsoc+ mpsoc芯片上，建议使用Mercury+ XU9模块上的硬件进行了验证。
Neuromorphic vision is a rapidly growing field with numerous applications in the perception systems of autonomous vehicles. Unfortunately, due to the sensors working principle, there is a significant amount of noise in the event stream. In this paper we present a novel algorithm based on an IIR filter matrix for filtering this type of noise and a hardware architecture that allows its acceleration using an SoC FPGA. Our method has a very good filtering efficiency for uncorrelated noise - over 99% of noisy events are removed. It has been tested for several event data sets with added random noise. We designed the hardware architecture in such a way as to reduce the utilisation of the FPGA's internal BRAM resources. This enabled a very low latency and a throughput of up to 385.8 MEPS million events per second.The proposed hardware architecture was verified in simulation and in hardware on the Xilinx Zynq Ultrascale+ MPSoC chip on the Mercury+ XU9 module with the Mercury+ ST1 base board.
