论文标题
低功率选项希腊人：使用FPGA的效率驱动的市场风险分析
Low-power option Greeks: Efficiency-driven market risk analysis using FPGAs
论文作者
论文摘要
定量金融是使用数学模型来分析金融市场和证券。通常需要大量的计算，一个重要的问题是新体系结构可以在加速这些模型中扮演的角色。在本文中，我们通过将Heston随机波动率模型以及Longstaff和Schwartz路径还原放置到Xilinx Alveo Alveo U280 FPGA上，探讨了行业标准证券技术分析中心（STAC）衍生物风险分析基准Stac-A2 \ TextTradeMark {}，并将其放置在Xilastaff和Schwartz路径上，并将其放置在Xilveo u280 fpga上。 详细描述为优化FPGA算法而采取的步骤，然后我们利用可重构体系结构提供的灵活性来探索围绕数值精度和表示形式的选择。然后在我们的最终性能和能量测量中利用获得的洞察力，在效率提高指标中，我们实现了FPGA的8倍至185倍，而两次24核Intel Xeon Platinum CPU。这项工作的结果不仅是用于FPGA的市场风险分析工作量的表演案例，而且还可以更广泛地将一套以效率驱动的技术和经验教训来应用于定量财务和计算工作负载。
Quantitative finance is the use of mathematical models to analyse financial markets and securities. Typically requiring significant amounts of computation, an important question is the role that novel architectures can play in accelerating these models. In this paper we explore the acceleration of the industry standard Securities Technology Analysis Center's (STAC) derivatives risk analysis benchmark STAC-A2\texttrademark{} by porting the Heston stochastic volatility model and Longstaff and Schwartz path reduction onto a Xilinx Alveo U280 FPGA with a focus on efficiency-driven computing. Describing in detail the steps undertaken to optimise the algorithm for the FPGA, we then leverage the flexibility provided by the reconfigurable architecture to explore choices around numerical precision and representation. Insights gained are then exploited in our final performance and energy measurements, where for the efficiency improvement metric we achieve between an 8 times and 185 times improvement on the FPGA compared to two 24-core Intel Xeon Platinum CPUs. The result of this work is not only a show-case for the market risk analysis workload on FPGAs, but furthermore a set of efficiency driven techniques and lessons learnt that can be applied to quantitative finance and computational workloads on reconfigurable architectures more generally.
