论文标题
CMOS兼容的ISING机器，使用通过铁电晶体管阵列构建的Bissable闩锁
CMOS-Compatible Ising Machines built using Bistable Latches Coupled through Ferroelectric Transistor Arrays
论文作者
论文摘要
实现与CMOS-Process技术兼容的紧凑型和可扩展的机器对于使用此类硬件平台加速计算上棘手的问题的有效性和实用性至关重要。除了需要实现紧凑的伊辛旋转外，描述旋转相互作用的耦合网络的实现也是此类平台可扩展性的潜在瓶颈。因此，在这项工作中，我们提出了一个ISING机器平台，该平台利用紧凑型双稳定CMOS束缚（交叉耦合逆变器）的新型行为，因为经典的Ising旋转通过高度可扩展的兼容和CMOS-PROCOSES兼容的Ferroelectric-HFO2基于基于CMOS-HFO2的CMOS-PROCESS旋转，基于基于Coupling elements的基于基于COUPLERTICTION cOUPLERTIENTS。我们通过实验证明了该系统的原型构建块，并使用模拟评估了缩放系统的行为。我们预测，所提出的体系结构可以计算效率约为1.04 x 10^8解决方案/w/sect的效率。我们的工作不仅为实现CMOS兼容的设计提供了一种途径，而且还可以克服他们的扩展挑战。
Realizing compact and scalable Ising machines that are compatible with CMOS-process technology is crucial to the effectiveness and practicality of using such hardware platforms for accelerating computationally intractable problems. Besides the need for realizing compact Ising spins, the implementation of the coupling network, which describes the spin interaction, is also a potential bottleneck in the scalability of such platforms. Therefore, in this work, we propose an Ising machine platform that exploits the novel behavior of compact bi-stable CMOS-latches (cross-coupled inverters) as classical Ising spins interacting through highly scalable and CMOS-process compatible ferroelectric-HfO2-based Ferroelectric FETs (FeFETs) which act as coupling elements. We experimentally demonstrate the prototype building blocks of this system, and evaluate the behavior of the scaled system using simulations. We project that the proposed architecture can compute Ising solutions with an efficiency of ~1.04 x 10^8 solutions/W/second. Our work not only provides a pathway to realizing CMOS-compatible designs but also to overcoming their scaling challenges.
