论文标题
通过使用神经网络推断硬件表演来实现最佳VPU编译器成本建模
Towards Optimal VPU Compiler Cost Modeling by using Neural Networks to Infer Hardware Performances
论文作者
论文摘要
计算神经网络编译器中最有效的工作时间表是一项艰巨的任务。需要考虑许多参数，可以根据其配置对该时间表产生积极或不利的影响 - 如何在分布式目标之间共享工作，该工作是如何在分布式目标之间共享的，张紧器的细分以适合记忆，切换优化的启用等等，传统上，神经网络编译器通过构建选择的选择值和选择的成本来确定如何设置这些价值，并选择了这些值，并选择了Minal'Mimal'Mimal'。这些选择及其相应的成本通常是由具有深入了解目标平台的工程师制作的算法确定的。但是，当编译器可用的选项量很大时，很难确保这些模型始终为所有方案提供最佳的时间表，同时仍在可接受的时间范围内完成编译。本文介绍了“ VPUNN” - 一种基于神经网络的成本模型，该模型在低级任务分析中培训，在英特尔的VPU处理器系列中持续优于最先进的成本建模。
Calculating the most efficient schedule of work in a neural network compiler is a difficult task. There are many parameters to be accounted for that can positively or adversely affect that schedule depending on their configuration - How work is shared between distributed targets, the subdivision of tensors to fit in memory, toggling the enablement of optimizations, etc. Traditionally, neural network compilers determine how to set these values by building a graph of choices and choosing the path with minimal 'cost'. These choices and their corresponding costs are usually determined by an algorithm crafted by engineers with a deep knowledge of the target platform. However, when the amount of options available to a compiler is large, it is very difficult to ensure that these models consistently produce an optimal schedule for all scenarios, whilst still completing compilation in an acceptable timeframe. This paper presents 'VPUNN' - a neural network-based cost model trained on low-level task profiling that consistently outperforms the state-of-the-art cost modeling in Intel's line of VPU processors.
