论文标题
对可靠系统的正式验证方法的调查
A Survey on Formal Verification Approaches for Dependable Systems
论文作者
论文摘要
在不同的安全至关重要应用（例如工业自动化，过程控制，运输和医疗数字设备）中，数字嵌入式系统的复杂性一直在增加。这些系统的正确操作在很大程度上依赖于嵌入式数字设备的行为。结果，在嵌入式设备的设计阶段犯的任何错误或错误都可以改变关键系统的整体功能并引起灾难性后果。为了检测这些错误并消除了它们对系统的影响，必须在数字系统的设计中创新新的错误检测方法。但是，这些方法需要巨大的成本和时间。用于解决此问题的这些方法之一称为验证和验证（V＆V），该方法确认系统行为在发展阶段之前符合开发过程的早期需求。由于它们在复杂数字系统的建设中的好处和重要性，因此，正式的V＆V方法的使用最近引起了很多关注。本文着重介绍有关正式验证方法的各种研究以及如何为开发高可靠的数字嵌入式系统而实现V＆V
The complexity of digital embedded systems has been increasing in different safety-critical applications such as industrial automation, process control, transportation, and medical digital devices. The correct operation of these systems relies too heavily on the behavior of the embedded digital device. As a result, any mistake or error made during the design stage of the embedded device can change the overall functionality of the critical system and cause catastrophic consequences. To detect these errors and eliminate their effects on the system, new error detection approaches must be innovated and used in the design of the digital system. However, these methods require enormous costs and time. One of these methods being employed to solve this issue is called Verification and Validation (V&V) which confirms that the system behavior meets the requirements early in the development process, before moving on to the implementation phase. Because of their benefits and importance in the building of complex digital systems, the employment of formal V&V methods has recently attracted a lot of attention. This paper focuses on presenting various studies on formal verification approaches and how the V&V can be achieved for developing high dependable digital embedded systems
