论文标题

Magnonic电路的表现会优于CMOS吗?

Would Magnonic Circuits Outperform CMOS Counterparts?

论文作者

Mahmoud, Abdulqader, Cucu-Laurenciu, Nicoleta, Vanderveken, Frederic, Ciubotaru, Florin, Adelmann, Christoph, Cotofana, Sorin, Hamdioui, Said

论文摘要

在新技术开发的早期阶段,很难对其潜在能力和影响进行全面评估。然而,可以得出一些初步估计,并且当然引起了人们的极大兴趣,在本文中,我们遵循自旋波(SW)计算范式框架内的这一推理。特别是,我们有兴趣评估需要达到的技术发展视野,以释放全部SW范式潜力,以便SW电路在能源消耗方面可以超越CMOS的表现。鉴于通过铁磁波导的零功率SWS传播,总体SW电路功率消耗取决于与SWS生成和通过传感器相关的传播。尽管当前的基于天线的传感器显然是饥饿的近期发展,表明磁电(ME)细胞具有超低功率SW产生和传感的巨大潜力。鉴于ME仅在概念水平上提出,并且没有报告实际的实验证明,我们无法评估其利用对SW电路能耗的影响。但是,我们可以执行反向工程分析,以确定可以将SW电路置于领先位置的延迟和功耗上限。为此,我们利用32位Brent-Kung加法器(BKA)作为讨论工具,并计算最大的延迟和功耗,这可能使SW实施能够超越其7NM CMOS的功能。我们评估了依赖转换或归一化门级联的不同BKA SW实现,并考虑连续或脉冲的SW发电场景。 31NW是32位BKA SW实施的最大传感器功耗可以优于其7nm CMOS的功能。

In the early stages of a novel technology development, it is difficult to provide a comprehensive assessment of its potential capabilities and impact. Nevertheless, some preliminary estimates can be drawn and are certainly of great interest and in this paper we follow this line of reasoning within the framework of the Spin Wave (SW) computing paradigm. In particular, we are interested in assessing the technological development horizon that needs to be reached in order to unleash the full SW paradigm potential such that SW circuits can outperform CMOS counterparts in terms of energy consumption. In view of the zero power SWs propagation through ferromagnetic waveguides, the overall SW circuit power consumption is determined by the one associated to SWs generation and sensing by means of transducers. While current antenna based transducers are clearly power hungry recent developments indicate that magneto-electric (ME) cells have a great potential for ultra-low power SW generation and sensing. Given that MEs have been only proposed at the conceptual level and no actual experimental demonstration has been reported we cannot evaluate the impact of their utilization on the SW circuit energy consumption. However, we can perform a reverse engineering alike analysis to determine ME delay and power consumption upper bounds that can place SW circuits in the leading position. To this end, we utilize a 32-bit Brent-Kung Adder (BKA) as discussion vehicle and compute the maximum ME delay and power consumption that could potentially enable a SW implementation able to outperform its 7nm CMOS counterpart. We evaluate different BKA SW implementations that rely on conversion or normalization gate cascading and consider continuous or pulsed SW generation scenarios. 31nW is the maximum transducer power consumption for which a 32-bit BKA SW implementation can outperform its 7nm CMOS counterpart.

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