论文标题
快速选择性冲洗以减轻基于竞争的缓存时间攻击
Fast Selective Flushing to Mitigate Contention-based Cache Timing Attacks
论文作者
论文摘要
缓存被广泛用于改善现代处理器的性能。通过仔细驱逐缓存线并识别缓存命中/错过时间，可以安排基于竞争的缓存正时频道攻击，以泄露受害者流程的信息。探索的高速缓存分区和随机化探索的现有硬件对策要么昂贵，不适用于L1数据缓存，要么容易受到复杂的攻击。存在使用缓存冲洗的对策，但速度很慢，因为在缓存过程中必须撤离所有缓存线。在本文中，我们首次提出了一个基于硬件/软件的基于齐平的对策，称为快速选择性冲洗（Fase）。通过利用ISA扩展名（一个冲洗指令）和缓存修改（附加状态位和控制逻辑），循环选择性地冲洗缓存线，并提供了一种缓解方法，具有与使用幼稚冲洗方法的现有方法相似的效果。 Fase在RISC-V Rocket Core/芯片上实施，并在Xilinx FPGA运行用户程序和Linux操作系统上进行了评估。我们的实验结果表明，与幼稚冲洗的方法相比，用户程序的FASE可显着减少36％的时间间接费用，而操作系统的时间间接费用为42％，而较小的硬件开销少于1％。我们的安全测试表明，FASE能够减轻目标缓存时间攻击。
Caches are widely used to improve performance in modern processors. By carefully evicting cache lines and identifying cache hit/miss time, contention-based cache timing channel attacks can be orchestrated to leak information from the victim process. Existing hardware countermeasures explored cache partitioning and randomization, are either costly, not applicable for the L1 data cache, or are vulnerable to sophisticated attacks. Countermeasures using cache flush exist but are slow since all cache lines have to be evacuated during a cache flush. In this paper, we propose for the first time a hardware/software flush-based countermeasure, called fast selective flushing (FaSe). By utilizing an ISA extension (one flush instruction) and cache modification (additional state bits and control logic), FaSe selectively flushes cache lines and provides a mitigation method with a similar effect to existing methods using naive flushing methods. FaSe is implemented on RISC-V Rocket Core/Chip and evaluated on Xilinx FPGA running user programs and the Linux operating system. Our experimental results show that FaSe reduces time overhead significantly by 36% for user programs and 42% for the operating system compared to the methods with naive flushing, with less than 1% hardware overhead. Our security test shows FaSe is capable of mitigating target cache timing attacks.
