论文标题
高度多重的超导检测器读数：平易近的高速FPGA设计
Highly-Multiplexed Superconducting Detector Readout: Approachable High-Speed FPGA Design
论文作者
论文摘要
这项工作介绍了高度多重的超导检测器读数的设计和初步性能。读取系统在Xilinx ZCU111 RFSOC评估板上实现。当前的设计使用12％的DSP，60％的LUTS，20％的FFS和30％的BRAM，并以512 MHz的速度进行计时。该系统使用以4.096 GSP运行的两个集成的ADC和DAC来读取2,048个超导检测器。这项工作的目标是每板处理的超导检测器数量增加2倍，其功率比以前的读数方案少80％。开源设计利用现代FPGA生产力工具，包括Vivado高级合成来创建所有自定义IP块，PYNQ来测试和验证单个IP并开发Python驱动程序，以及Vivado ML智能设计运行以接近时机。我们强调没有自定义HDL实现时机关闭的策略，我们希望这对于希望在没有FPGA设计专业知识的情况下利用FPGA的超导设备组有用。
This work presents the design and preliminary performance of a highly-multiplexed superconducting detector readout. The readout system is implemented on the Xilinx ZCU111 RFSoC Evaluation Board. The current design uses 12% of the DSPs, 60% of the LUTs, 20% of the FFs, and 30% of the BRAM and makes timing at 512 MHz. The system uses two integrated ADCs and DACs running at 4.096 GSPS to read out 2,048 superconducting detectors. This work targets a 2x increase in the number of superconducting detectors processed per board with 80% less power than previous readout schemes. The open-source design leverages modern FPGA productivity tools including Vivado High-Level Synthesis to create all custom IP blocks, PYNQ to test and verify individual IP and develop Python drivers, and Vivado ML Intelligent Design Runs to close timing. We emphasize strategies for achieving timing closure without custom HDL which we expect to be useful for superconducting device groups looking to utilize FPGAs in high-performance applications without specialized knowledge in FPGA design.
