论文标题
DWM转移的固定故障模式建模
Pinning Fault Mode Modeling for DWM Shifting
论文作者
论文摘要
极限缩放是为了达到更高密度和较低能量的目的，继续增加记忆故障的可能性。对于域壁（DW）记忆，当将域与访问点对齐时会出现错位故障。先前研究的转移断层类型，可能会导致固定故障，这是由于由具有制造缺陷的缺口引起的不均匀固定电势分布。这种不均匀性可以在电流引起的DW运动期间固定壁。本文提供了一种几何变化模型，其凹槽的宽度，深度和曲率变化，它们对临界偏移电流的影响以及对DW内存系统故障率的影响的研究。由于5％变化而导致的有效临界偏移电流的增加预测，每移$ 10^{ - 8} $的固定断层率，导致DW内存系统的平均时间到2S。
Extreme scaling for purposes of achieving higher density and lower energy continues to increase the probability of memory faults. For domain wall (DW) memories, misalignment faults arise when aligning domains with access points. A previously understudied type of shifting fault, a pinning fault may occur due to non-uniform pinning potential distribution caused by notches with fabrication imperfections. This non-uniformity can pin a wall during current-induced DW motion. This paper provides a model of geometric variations varying width, depth, and curvature variations of a notch, their impacts on the critical shift current, and a study of the resulting impact on fault rates of DW memory systems. An increase in the effective critical shift current due to 5% variation predicts a pinning fault rate on the order of $10^{-8}$ per shift, which results in a mean-time-to-failure of circa 2s for a DW memory system.
