论文标题
轻巧的软误差弹性适应处固定核心
Lightweight Soft Error Resilience for In-Order Cores
论文作者
论文摘要
基于声传感器的软误差弹性弹性弹性特别有希望，因为它可以验证没有软错误并以低硬件成本消除无声数据损坏。但是，由于验证过程中频繁的结构/数据危害，最先进的工作会为内核带来明显的性能开销。为了解决该问题，本文提出了Turnpike，这是一种编译器/体系结构共同设计方案，可以实现轻巧但可以保证的固定核心软误差弹性。关键思想是，在核心中计算出的许多数据都可以绕过软误差验证，而不会损害弹性。除了简单的微构造支持以实现这个想法，收费公路利用了编译器优化，以进一步降低性能开销。 36个基准测试的实验结果表明，当基于传感器的误差检测最严重的延迟为10-50周期时，收费公路的平均开销只会造成0-14％的运行时间开销，而最先进的开头会造成29-84％的开销。
Acoustic-sensor-based soft error resilience is particularly promising, since it can verify the absence of soft errors and eliminate silent data corruptions at a low hardware cost. However, the state-of-the-art work incurs a significant performance overhead for in-order cores due to frequent structural/data hazards during the verification. To address the problem, this paper presents Turnpike, a compiler/architecture co-design scheme that can achieve lightweight yet guaranteed soft error resilience for in-order cores. The key idea is that many of the data computed in the core can bypass the soft error verification without compromising the resilience. Along with simple microarchitectural support for realizing the idea, Turnpike leverages compiler optimizations to further reduce the performance overhead. Experimental results with 36 benchmarks demonstrate that Turnpike only incurs a 0-14% run-time overhead on average while the state-of-the-art incurs a 29-84% overhead when the worst-case latency of the sensor based error detection is 10-50 cycles.
