论文标题
基于仿真的基于SystemC的VPS在ESL上的验证
Simulation-based Verification of SystemC-based VPs at the ESL
论文作者
论文摘要
半导体行业越来越多地采用了电子系统级别（ESL）的基于SystemC的虚拟原型（VP）。主要原因是VP较早可用，它们的模拟是与较低抽象级别（例如RTL）的硬件模型相比，数量级更快。这使设计人员使用VPS作为早期设计验证的参考模型。因此，VP的正确性至关重要，因为未发现的错误可能会在设计过程中传播到较少的抽象级别，从而增加了固定成本和精力。在本文中，我们引入了一种基于仿真的验证方法，以自动验证给定SystemC VP的模拟行为，以针对TLM-2.0规则及其规格，即通信在VP中的功能和时机行为。
SystemC-based Virtual Prototypes (VPs) at the Electronic System Level (ESL) are increasingly adopted by the semiconductor industry. The main reason is that VPs are much earlier available, and their simulation is orders of magnitude faster in comparison to the hardware models at lower levels of abstraction (e.g. RTL). This leads designers to use VPs as reference models for early design verification. Hence, the correctness of VPs is of utmost importance as undetected errors may propagate to less abstract levels in the design process, increasing the fixing cost and effort. In this paper, we introduce a comprehensive simulation-based verification approach to automatically validate the simulation behavior of a given SystemC-based VP against both the TLM-2.0 rules and its specifications, i.e. functional and timing behavior of communications in the VP.
