论文标题
玫瑰花蕾：使FPGA加速中间箱开发更令人愉悦
Rosebud: Making FPGA-Accelerated Middlebox Development More Pleasant
论文作者
论文摘要
我们介绍了一种设计FPGA加速中间箱的方法，该方法通过解开硬件加速器实现和软件应用程序的任务来简化开发，调试和性能调整。 Rosebud是通过标准化的硬件/软件接口将硬件加速器连接到高性能数据包处理管道的框架。这种关注点的分离使硬件开发人员可以专注于优化自定义加速器，同时释放软件程序员以类似于软件库的方式重复使用，配置和调试加速器。我们通过建造基于大型黑名单的防火墙，并在不到一个月的时间内将Pigasus IDS模式匹配加速器移植，从而展示了玫瑰花蕾框架的好处。我们的实验表明，玫瑰花蕾提供了高性能，可提供约200英镑的流量，同时仅增加0.7-7微秒的延迟。
We introduce an approach to designing FPGA-accelerated middleboxes that simplifies development, debugging, and performance tuning by decoupling the tasks of hardware-accelerator implementation and software-application programming. Rosebud is a framework that links hardware accelerators to a high-performance packet processing pipeline through a standardized hardware/software interface. This separation of concerns allows hardware developers to focus on optimizing custom accelerators while freeing software programmers to reuse, configure, and debug accelerators in a fashion akin to software libraries. We show the benefits of the Rosebud framework by building a firewall based on a large blacklist and porting the Pigasus IDS pattern-matching accelerator in less than a month. Our experiments demonstrate that Rosebud delivers high performance, serving ~200 Gbps of traffic while adding only 0.7-7 microseconds of latency.
