论文标题
基于PDSE2的现场效应晶体管
PdSe2 based field-effect transistors
论文作者
论文摘要
五角形PDSE2是层次电子设备的有前途的候选者,这是由于其高空气稳定性和各向异性传输特性。在这里,我们使用多尺度仿真框架结合了密度功能理论和量子传输的多尺度仿真框架,研究了基于PDSE $ _2 $单层的P型FET的性能。我们发现,对于沿[010]和[100]方向对齐的源限制方向,单层PDSE $ _2 $设备显示出出色的切换特性($ <$ 65 mv/dec)。这两个方向还显示出良好的状态电流和较大的跨导率,尽管对于15 nm通道设备的[010]方向沿[010]方向较大。这些P-FET的通道长度缩放研究表明,通道长度可以轻松缩小到7 nm,而不会在性能中造成任何损害。低于7 nm,我们发现在4 nm的通道长度上,亚阈值秋千存在严重的降解。但是,可以通过引入底层结构来最大程度地减少这种降解。底板的长度取决于州内电流和切换性能之间的权衡。
Pentagonal PdSe2 is a promising candidate for layered electronic devices, owing to its high air-stability and anisotropic transport properties. Here, we investigate the performance of p-type FET based on PdSe$_2$ mono-layer using multi-scale simulation framework combining Density functional theory and quantum transport. We find that mono-layer PdSe$_2$ devices show excellent switching characteristics ($<$ 65 mV/decade) for the source-drain direction aligned along both [010] and [100] directions. Both directions also show good on-state current and large transconductance, though these are larger along the [010] direction for a 15 nm channel device. The channel length scaling study of these p-FETs indicates that channel length can be easily scaled down to 7 nm without any significance compromise in the performance. Going below 7 nm, we find that there is a severe degradation in the sub-threshold swing for 4 nm channel length. However, this degradation can be minimized by introducing an underlap structure. The length of underlap is determined by the trade-off between on-state current and the switching performance.