论文标题
对ECC的水平攻击：从模拟到ASIC
Horizontal Attacks against ECC: from Simulations to ASIC
论文作者
论文摘要
在本文中，我们分析了不同编译选项对侧通道分析攻击成功率的影响。我们对合成后和布局后使用两个不同的编译选项合成的相同$ kp $ design合成的相同$ kp $设计的模拟功率迹线进行水平差分侧通道攻击。由于我们对生产的ASIC的影响感兴趣，因此在制造ASIC后，对测得的功率痕迹也会进行相同的攻击。我们发现，与简单的编译选项相比，Compile_ultra选项从5位关键候选人中显着降低了75％至90％的关键候选者，最大成功率为72％，最大成功率为72％。另外，布局后的成功率与攻击测得的功率和电磁痕迹的成功率非常高，即模拟是ASIC电阻的良好指标。
In this paper we analyse the impact of different compile options on the success rate of side-channel analysis attacks. We run horizontal differential side-channel attacks against simulated power traces for the same $kP$ design synthesized using two different compile options after synthesis and after layout. As we are interested in the effect on the produced ASIC we also run the same attack against measured power traces after manufacturing the ASIC. We found that the compile_ultra option reduces the success rate significantly from 5 key candidates with a correctness of between 75 and 90 per cent down to 3 key candidates with a maximum success rate of 72 per cent compared to the simple compile option. Also the success rate after layout shows a very high correlation with the one obtained attacking the measured power and electromagnetic traces, i.e. the simulations are a good indicator of the resistance of the ASIC.
