论文标题
DR-STRANGE：基于DRAM的真实随机数生成器的端到端系统设计
DR-STRaNGe: End-to-End System Design for DRAM-based True Random Number Generators
论文作者
论文摘要
在各种关键应用中，随机数是一项重要的任务，包括加密算法，科学模拟和工业测试工具。真实的随机数生成器（TRNG）通过对通常需要自定义硬件并遭受较长延迟的物理熵源来产生真正的随机数据。为了在商品设备上实现高带宽和低延迟TRNG，最近的作品提出了将DRAM用作熵源的TRNG。尽管先前的工作表明了有希望的基于DRAM的TRNG，但将这种机制集成到真实系统中却带来了挑战。 We identify three challenges for using DRAM-based TRNGs in current systems: (1) generating random numbers can degrade system performance by slowing down concurrently-running applications due to the interference between RNG and regular memory operations in the memory controller (i.e., RNG interference), (2) this RNG interference can degrade system fairness by unfairly prioritizing applications that intensively use random numbers (i.e., RNG applications), and （3）由于较高的RNG延迟，RNG应用程序可能会遇到明显的放缓。我们提出了DR-STRANGE，这是一种针对DRAM TRNG的端到端系统设计，（1）通过将RNG请求与内存控制器中的定期请求分开来减少RNG干扰，（2）使用RNG Aware Aware Aware Aware Memory请求来改善系统的公平性，并使用大型TRNG LAUDERISE ID藏书，以预测较大的TRNG LEADERISION，并将其确定为新的DRAM，以确定较大的TRNG LEADERIFERS IDIFTAINS NEW DRAMISS IDLAM， DRAM时期。我们使用一组186个多编程工作负载评估DR-Trange。与符合RNG的基线系统相比，DR-STRANGE分别将非RNG和RNG应用程序的平均性能提高了17.9％和25.1％。 DR-Trange将平均系统公平性提高了32.1％，并将平均能源消耗降低了21％。
Random number generation is an important task in a wide variety of critical applications including cryptographic algorithms, scientific simulations, and industrial testing tools. True Random Number Generators (TRNGs) produce truly random data by sampling a physical entropy source that typically requires custom hardware and suffers from long latency. To enable high-bandwidth and low-latency TRNGs on commodity devices, recent works propose TRNGs that use DRAM as an entropy source. Although prior works demonstrate promising DRAM-based TRNGs, integration of such mechanisms into real systems poses challenges. We identify three challenges for using DRAM-based TRNGs in current systems: (1) generating random numbers can degrade system performance by slowing down concurrently-running applications due to the interference between RNG and regular memory operations in the memory controller (i.e., RNG interference), (2) this RNG interference can degrade system fairness by unfairly prioritizing applications that intensively use random numbers (i.e., RNG applications), and (3) RNG applications can experience significant slowdowns due to the high RNG latency. We propose DR-STRaNGe, an end-to-end system design for DRAM-based TRNGs that (1) reduces the RNG interference by separating RNG requests from regular requests in the memory controller, (2) improves the system fairness with an RNG-aware memory request scheduler, and (3) hides the large TRNG latencies using a random number buffering mechanism with a new DRAM idleness predictor that accurately identifies idle DRAM periods. We evaluate DR-STRaNGe using a set of 186 multiprogrammed workloads. Compared to an RNG-oblivious baseline system, DR-STRaNGe improves the average performance of non-RNG and RNG applications by 17.9% and 25.1%, respectively. DR-STRaNGe improves average system fairness by 32.1% and reduces average energy consumption by 21%.
