论文标题
重复使用验证声明作为硬件特洛伊木马检测的安全检查器
Reusing Verification Assertions as Security Checkers for Hardware Trojan Detection
论文作者
论文摘要
半导体行业的全球化使Fabress设计公司能够降低其成本，节省时间并利用较新的技术。但是，集成电路（IC）制造的离岸外包具有负面的方面，包括诸如硬件特洛伊木马（HTS）之类的威胁 - 一种恶意逻辑，并不容易检测。不受全球化影响的IC设计的一个方面是需要进行彻底验证。验证工程师设计了复杂的资产，以确保设计无漏洞，包括断言。验证结束后，通常不会重复使用这些知识。本文的前提是，可以将已经存在的验证资产转变为有效的安全检查器以进行HT检测。为此，我们展示了如何将断言用作在线监视器。为此，我们提出了一个利用Cadence jaspergold安全路径验证（SPV）的确保度量和断言选择流。实验结果表明，我们通过分析Opentitan System-on-Chip（SOC）的不同智力特性（IPS）的100多个主张，通过分析了100多个智力特性（IPS）的范围。此外，我们的检测解决方案是务实的，因为它不依赖于HT激活机制。
Globalization in the semiconductor industry enables fabless design houses to reduce their costs, save time, and make use of newer technologies. However, the offshoring of Integrated Circuit (IC) fabrication has negative sides, including threats such as Hardware Trojans (HTs) - a type of malicious logic that is not trivial to detect. One aspect of IC design that is not affected by globalization is the need for thorough verification. Verification engineers devise complex assets to make sure designs are bug-free, including assertions. This knowledge is typically not reused once verification is over. The premise of this paper is that verification assets that already exist can be turned into effective security checkers for HT detection. For this purpose, we show how assertions can be used as online monitors. To this end, we propose a security metric and an assertion selection flow that leverages Cadence JasperGold Security Path Verification (SPV). The experimental results show that our approach scales for industry-size circuits by analyzing more than 100 assertions for different Intellectual Properties (IPs) of the OpenTitan System-on-Chip (SoC). Moreover, our detection solution is pragmatic since it does not rely on the HT activation mechanism.
