论文标题
使用机器学习优化设计验证：开源解决方案
Optimising Design Verification Using Machine Learning: An Open Source Solution
论文作者
论文摘要
随着集成电路的复杂性的增加，设计验证已成为ASIC设计流中最耗时的部分。 SOC设计周期的近70％是通过验证消耗的。测试所有转角案例的最常用方法是使用受约束的随机验证。给出随机刺激，以达到所有可能的组合并彻底测试设计。但是，这种方法通常需要大量的人类专业知识才能达到所有角落案例。本文提出了一种使用机器学习来产生输入刺激的替代方案。这将允许更快的人进行干预，对设计进行更快的透彻验证。此外，建议使用开源验证环境“ Cocotb”。基于Python，它很简单，直观，并且在机器学习应用程序中拥有庞大的功能库。这使使用传统硬件验证语言（例如System Verilog或SpecmanE）的批量方法更方便使用。
With the complexity of Integrated Circuits increasing, design verification has become the most time consuming part of the ASIC design flow. Nearly 70% of the SoC design cycle is consumed by verification. The most commonly used approach to test all corner cases is through the use of Constrained Random Verification. Random stimulus is given in order to hit all possible combinations and test the design thoroughly. However, this approach often requires significant human expertise to reach all corner cases. This paper presents an alternative using Machine Learning to generate the input stimulus. This will allow for faster thorough verification of the design with less human intervention. Furthermore, it is proposed to use the open source verification environment 'Cocotb'. Based on Python, it is simple, intuitive and has a vast library of functions for machine learning applications. This makes it more convenient to use than the bulkier approach using traditional Hardware Verification Languages such as System Verilog or Specman E.
