论文标题
RVCorep-32IC：高性能RISC-V软处理器，具有高效提取单元，支持压缩说明
RVCoreP-32IC: A high-performance RISC-V soft processor with an efficient fetch unit supporting the compressed instructions
论文作者
论文摘要
在本文中，我们提出了一个高性能RISC-V软处理器，其有效的提取单元支持针对FPGA的压缩说明。 RISC-V中的压缩说明扩展可以将程序规模降低约25％。但是它需要复杂的逻辑来提取单元，并对性能产生重大影响。我们提出了一个指令提取单元，该单元在表现出高性能的同时支持压缩说明。此外，我们建议使用此单元提出一个RISC-V软处理器。我们在Verilog HDL中实现了该提出的处理器，并使用Verilog模拟和实际的Xilinx Atrix-7 FPGA板验证了行为。我们将一些基准的结果和硬件数量与相关工作进行比较。提议的处理器的DMIP，赛车价值和嵌入值分别比相关工作高42.5％，41.1％和21.3％。
In this paper, we propose a high-performance RISC-V soft processor with an efficient fetch unit supporting the compressed instructions targeting on FPGA. The compressed instruction extension in RISC-V can reduce the program size by about 25%. But it needs a complicated logic for the instruction fetch unit and has a significant impact on performance. We propose an instruction fetch unit that supports the compressed instructions while exhibiting high performance. Furthermore, we propose a RISC-V soft processor using this unit. We implement this proposed processor in Verilog HDL and verify the behavior using Verilog simulation and an actual Xilinx Atrix-7 FPGA board. We compare the results of some benchmarks and the amount of hardware with related works. DMIPS, CoreMark value, and Embench value of the proposed processor achieved 42.5%, 41.1% and 21.3% higher performance than the related work, respectively.
