论文标题
RISC-V SystemC-TLM模拟器
A RISC-V SystemC-TLM simulator
论文作者
论文摘要
这项工作为RISC-V微控制器提供了基于SystemC-TLM的模拟器。该模拟器专注于简单性，易于扩展RISC-V。它是围绕完整的RISC-V指令集模拟器构建的，该模拟器支持完整的RISC-V ISA和扩展M，A，C，ZICSR和Zifencei。 ISS封装在TLM-2包装器中，使其能够与任何其他TLM-2兼容模块进行通信。模拟器还包括一组非常基本的外围设备，以启用完整的SOC模拟器。可以使用标准工具来编译运行代码，并使用标准的C库而无需修改。模拟器能够正确执行RISCV合并套件。整个模拟器作为Docker映像发布，以简化开发人员的安装和使用。还发布了模拟SOC的FreertoSv10.2.1的移植。
This work presents a SystemC-TLM based simulator for a RISC-V microcontroller. This simulator is focused on simplicity and easy expandable of a RISC-V. It is built around a full RISC-V instruction set simulator that supports full RISC-V ISA and extensions M, A, C, Zicsr and Zifencei. The ISS is encapsulated in a TLM-2 wrapper that enables it to communicate with any other TLM-2 compatible module. The simulator also includes a very basic set of peripherals to enable a complete SoC simulator. The running code can be compiled with standard tools and using standard C libraries without modifications. The simulator is able to correctly execute the riscv-compliance suite. The entire simulator is published as a docker image to ease its installation and use by developers. A porting of FreeRTOSv10.2.1 for the simulated SoC is also published.
