论文标题
在Kintex-7 FPGA上实现的高分辨率多相时钟时间数字转换器
A high resolution multi-phase clock Time-Digital Convertor implemented on Kintex-7 FPGA
论文作者
论文摘要
时数转换器（TDC）旨在测量脉冲信号前缘的到达时间。我们最近的工作提出了基于Kintex-7字段可编程栅极阵列（FPGA）设备的高分辨率多相TDC。简单的基于I/O瓷砖的圆形输入缓冲区用于定期振荡输入信号，然后使用基于ISERDES CORE的多相TDC，使用625 PS bin尺寸来完成多个测量，以获得更高的分辨率性能。在本文中，讨论了设计概念，体系结构以及内核实施注意事项。为了评估TDC的性能，我们建立了基于Kintex-7 FPGA的验证系统。初始测试结果表明，TDC的有效箱大小从625 PS成功降低到78.125 PS，并且测得的双通道时间分辨率优于35 PS RMS。
Time-digital Converter (TDC) aims to measure the arrival time of the leading edge of the pulse signal. Our recent work presented a high resolution multi-phase TDC based on the Kintex-7 Field Programmable Gate Array (FPGA) device. A simple I/O tile based circular input buffer is employed to oscillate the input signal periodically, and then a multi-phase TDC based on ISERDES core with a 625 ps bin size is used to accomplish the multiple measurements for getting higher resolution performance. In this paper, the design concept, architecture, as well as kernel implementation considerations are all discussed. To evaluate the TDC's performance, we built a verification system based on Kintex-7 FPGA. Initial test results indicate that the TDC's effective bin size is successfully reduced from 625 ps to 78.125 ps, and the measured dual-channel time resolution is better than 35 ps RMS.
