论文标题
具有快速模块化乘法的嵌入式RISC-V核
An Embedded RISC-V Core with Fast Modular Multiplication
论文作者
论文摘要
物联网中最大的担忧之一是隐私和安全。加密和身份验证需要大功率预算，电池操作的物联网末端节点没有。为特定的加密操作设计的硬件加速器几乎没有灵活性的未来更新。自定义指示解决方案的区域较小，并为实施新方法提供了更大的灵活性。自定义说明的一个缺点是处理器必须等待操作完成。最终，设备对实时事件的响应时间越来越长。在这项工作中，我们为模块化乘法提出了一个带有扩展自定义指令的处理器，该处理器在部分执行模式中使用时，通常将处理器（通常是两个模块化乘法）的两个循环。我们为概念证明CPU采用了RISC-V的嵌入式和压缩扩展。我们的设计基于椭圆曲线密码学领域的最近加密算法的基准测试。我们具有128位模块化乘法的CPU在ASIC上的136MHz和FPGA上的81MHz工作。它在软件实施方面达到了13倍的速度，同时将总体功耗降低了95 \％，而基本体系结构的平均面积为41 \％。
One of the biggest concerns in IoT is privacy and security. Encryption and authentication need big power budgets, which battery-operated IoT end-nodes do not have. Hardware accelerators designed for specific cryptographic operations provide little to no flexibility for future updates. Custom instruction solutions are smaller in area and provide more flexibility for new methods to be implemented. One drawback of custom instructions is that the processor has to wait for the operation to finish. Eventually, the response time of the device to real-time events gets longer. In this work, we propose a processor with an extended custom instruction for modular multiplication, which blocks the processor, typically, two cycles for any size of modular multiplication when used in Partial Execution mode. We adopted embedded and compressed extensions of RISC-V for our proof-of-concept CPU. Our design is benchmarked on recent cryptographic algorithms in the field of elliptic-curve cryptography. Our CPU with 128-bit modular multiplication operates at 136MHz on ASIC and 81MHz on FPGA. It achieves up to 13x speed up on software implementations while reducing overall power consumption by up to 95\% with 41\% average area overhead over our base architecture.
