论文标题
Xilinx基于28/60〜GHz无线测试床的基于RF-SOC的数字多光束阵列处理器
Xilinx RF-SoC-based Digital Multi-Beam Array Processors for 28/60~GHz Wireless Testbeds
论文作者
论文摘要
新兴的无线应用，例如5G蜂窝，大型智能表面（LIS）和全息巨型MIMO，需要具有大量独立数字收发器的MM波频率的天线阵列处理。本文总结了作者在基于宽带可重构FPGA基于FPGA的软件定义的无线电（SDRS）的28 GHz和60 GHz全位数阵列处理平台上的设计和测试方面的最新进展。 SDR的数字基带和微波接口方面是在Xilinx的单芯片RF System-Chip（RF-SOC）处理器上实现的。 RF-SOC技术的两个版本（ZCU-111和ZCU-1275）用于在28〜GHz处实现完全数字的实时阵列处理器（实现4个平行梁，每光束0.8 GHz带宽）和60 〜GHz（实现4个平行梁，每光束1.8〜GHz带束带）。提出了位于焦平面上的数字阶梯阵列（PAF）喂养的介电透镜阵列，以进一步增加天线阵列增益。
Emerging wireless applications such as 5G cellular, large intelligent surfaces (LIS), and holographic massive MIMO require antenna array processing at mm-wave frequencies with large numbers of independent digital transceivers. This paper summarizes the authors' recent progress on the design and testing of 28 GHz and 60 GHz fully-digital array processing platforms based on wideband reconfigurable FPGA-based software-defined radios (SDRs). The digital baseband and microwave interfacing aspects of the SDRs are implemented on single-chip RF system-on-chip (RF-SoC) processors from Xilinx. Two versions of the RF-SoC technology (ZCU-111 and ZCU-1275) were used to implement fully-digital real-time array processors at 28~GHz (realizing 4 parallel beams with 0.8 GHz bandwidth per beam) and 60~GHz (realizing 4 parallel beams with 1.8~GHz bandwidth per beam). Dielectric lenslet arrays fed by a digital phased-array feed (PAF) located on the focal plane are proposed for further increasing antenna array gain.
