论文标题
设计优化的部分重新配置
Partial Reconfiguration for Design Optimization
论文作者
论文摘要
传统上，FPGA设计师与ASIC设计师共享了类似的设计方法。最值得注意的是，在设计时，FPGA设计师承诺将逻辑资源分配给设计中的模块。在运行时，由于难以避免的效率来源（例如，操作依赖关系），某些被占用的资源可能会闲置或不足。通过部分重新配置（PR），可以随着时间的推移重新分配FPGA资源。因此，使用PR，设计师可以尝试通过更好的区域时间调度来减少空闲度和利用不足。 在本文中，我们解释了PR风格的设计何时，如何以及为什么可以在ASIC风格设计的性能区域（无PR）上改进。我们首先介绍了区域时间量的概念，以解释为什么PR风格的设计可以改善ASIC风格的设计。我们将利用不足的资源确定为可以通过PR风格设计利用的机会。然后，我们提出一个一阶分析模型，以帮助设计师确定PR风格的设计是否有益。在这种情况下，该模型指出了最合适的PR执行策略，并提供了改进的估计。该模型在三个案例研究中得到了验证。
FPGA designers have traditionally shared a similar design methodology with ASIC designers. Most notably, at design time, FPGA designers commit to a fixed allocation of logic resources to modules in a design. At runtime, some of the occupied resources could be left idle or under-utilized due to hard-to-avoid sources of inefficiencies (e.g., operation dependencies). With partial reconfiguration (PR), FPGA resources can be re-allocated over time. Therefore, using PR, a designer can attempt to reduce idleness and under-utilization with better area-time scheduling. In this paper, we explain when, how, and why PR-style designs can improve over the performance-area Pareto front of ASIC-style designs (without PR). We first introduce the concept of area-time volume to explain why PR-style designs can improve upon ASIC-style designs. We identify resource under-utilization as an opportunity that can be exploited by PR-style designs. We then present a first-order analytical model to help a designer decide if a PR-style design can be beneficial. When it is the case, the model points to the most suitable PR execution strategy and provides an estimate of the improvement. The model is validated in three case studies.
