论文标题
具有序列重复节点的高通量快速SSC极性解码器的实现
Implementation of a High-Throughput Fast-SSC Polar Decoder with Sequence Repetition Node
论文作者
论文摘要
即使最新5G细胞标准中采用了极地代码，它们仍然存在高解码延迟的基本问题。为了解决此问题，最近在\ cite {sr2020}中提出了基于新的序列重复（SR）节点的快速简化连续的取消（FAST-SSC）解码器，并且比其他现有的FAST-SSC解码器在理论中比其他现有的FASTSSC解码器的时间步骤较低。本文重点介绍了此基于SR节点的FAST-SSC（SRFSC）解码器的硬件实现。具有长度1024和代码速率1/2的极性代码的实现结果表明，在Altera Stratix IV FPGA上，我们的实施情况为$ 505 $ Mbps，相对于以前的工作，该吞吐量高17.9％。
Even though polar codes were adopted in the latest 5G cellular standard, they still have the fundamental problem of high decoding latency. Aiming at solving this problem, a fast simplified successive cancellation (Fast-SSC) decoder based on the new class of sequence repetition (SR) nodes has been proposed recently in \cite{sr2020} and has a lower required number of time steps than other existing Fast-SSC decoders in theory. This paper focuses on the hardware implementation of this SR node-based fast-SSC (SRFSC) decoder. The implementation results for a polar code with length 1024 and code rate 1/2 show that our implementation has a throughput of $505$ Mbps on an Altera Stratix IV FPGA, which is 17.9% higher with respect to the previous work.
