论文标题
LITEX：基于Migen Python DSL的开源SoC构建器和图书馆
LiteX: an open-source SoC builder and library based on Migen Python DSL
论文作者
论文摘要
Litex是一个github托管的SOC构建器 / IP库和实用程序，可用于创建SOC和完整的FPGA设计。除了获得开源和BSD许可之外，其独创性还在于，使用Migen Python Internalt DSL完全描述了其IP组件，从而简化了其设计深度。 Litex已经支持各种软核CPU和基本外围设备，而对专有IP块或发电机没有依赖性。本文提供了Litex的概述：介绍了FPGA上的两个真正的SOC设计。他们都利用Litex方法在设计条目，库和集成功能方面。第一个基于RISC-V核心，而第二个基于LM32核心。在第二种用例中，我们进一步证明了使用完全开源工具链和Litex的使用。
LiteX is a GitHub-hosted SoC builder / IP library and utilities that can be used to create SoCs and full FPGA designs. Besides being open-source and BSD licensed, its originality lies in the fact that its IP components are entirely described using Migen Python internal DSL, which simplifies its design in depth. LiteX already supports various softcores CPUs and essential peripherals, with no dependencies on proprietary IP blocks or generators. This paper provides an overview of LiteX: two real SoC designs on FPGA are presented. They both leverage the LiteX approach in terms of design entry, libraries and integration capabilities. The first one is based on RISC-V core, while the second is based on a LM32 core. In the second use case, we further demonstrate the use of a fully open-source toolchain coupled with LiteX.
