论文标题
在深度神经网络的硬件加速器设计中使用近似电路的库
Using Libraries of Approximate Circuits in Design of Hardware Accelerators of Deep Neural Networks
论文作者
论文摘要
已经开发了近似电路，以在错误弹性应用中（例如深神经网络的硬件加速器（DNN））中提供良好的权衡和服务质量之间的良好权衡。为了加速近似电路设计过程并支持电路近似方法的公平基准测试，已经引入了近似电路的库。例如，evoapprox8b包含数百个8位近似添加剂和乘数。通过基因编程，我们生成了库的扩展版本，其中包括数千个8至128位近似算术电路。这些电路相对于几个误差指标，功耗和其他电路参数形成了帕累托前部。在我们的案例研究中，我们展示了如何使用大量近似乘数来对Resnet DNN的硬件加速器进行弹性分析，并为给定应用程序选择最合适的近似乘数。报告了对CIFAR-10基准问题培训的RESNET DNN的各种实例的结果。
Approximate circuits have been developed to provide good tradeoffs between power consumption and quality of service in error resilient applications such as hardware accelerators of deep neural networks (DNN). In order to accelerate the approximate circuit design process and to support a fair benchmarking of circuit approximation methods, libraries of approximate circuits have been introduced. For example, EvoApprox8b contains hundreds of 8-bit approximate adders and multipliers. By means of genetic programming we generated an extended version of the library in which thousands of 8- to 128-bit approximate arithmetic circuits are included. These circuits form Pareto fronts with respect to several error metrics, power consumption and other circuit parameters. In our case study we show how a large set of approximate multipliers can be used to perform a resilience analysis of a hardware accelerator of ResNet DNN and to select the most suitable approximate multiplier for a given application. Results are reported for various instances of the ResNet DNN trained on CIFAR-10 benchmark problem.
